1. Field of the Present Invention
The present invention generally relates to the field of digital circuits and more particularly to an adder circuit that facilitates computations in an arithmetic unit of a microprocessor.
2. History of Related Art
Carry lookahead adders (CLA) are widely implemented in arithmetic units of microprocessors and other data processing devices. In a CLA, carry bits are computed algorithmically to reduce the propagation delay associated with a full n-bit adder in which determining the sum of high order bits must await the computation of low order carry bits. CLAs are more fully described in Hennessy & Patterson, Computer Architecture A Quantitative Approach Second Edition, Appendix A.8 (Morgan Kaufmann 1996) [hereinafter referred to as “Hennessy”].
In a CLA, the determination of the carry bit(s) is in the critical path. In other words, the performance of the adder is limited by the time required to generate the carry bit. In a conventional implementation, CLA circuits typically employ complementary pass-gate logic (CPL). In CPL design, logic gates are implemented with transistors of a single polarity (typically n-channel) while transistors of the opposite polarity may be used to reduce the circuit's static current.
Referring to FIG. 11, an exclusive-or (EXOR) circuit 10 is depicted as implemented with a conventional CPL design. Circuit 10 receives input signals “a” and “b” and their corresponding complements (indicated by the apostrophe mark). The “a” signal is connected to the gate electrodes of n-channel transistors 12 and 14 while the a′ signal is connected to the gate electrodes of n-channel transistors 16 and 18. The “b” signal is connected to the source electrode of transistors 14 and 16 while the “b′” signal is connected to the source electrode of transistors 12 and 18. The drain terminals of transistors 12 and 16 are tied together at node 20 while the drain terminals of transistors 14 and 18 are tied together at node 22. It can be easily verified that node 20 is the exclusive-or (EXOR) of signals “a” and “b” while node 22 is the negated EXOR (EXNOR). CPL circuit 10 further includes cross-coupled p-channel transistors connected to nodes 20 and 22 to reduce static current by imposing a high impedance channel between the power supply and the logically low input signal.
When a logical “1” is passed through the source/drain of an n-channel transistor in a CPL circuit, a voltage of Vdd-Vtn is produced where Vdd is the supply voltage and Vtn is the n-channel threshold voltage. This passed voltage may be restored using an inverter having relatively weak p-channel device and a relatively strong n-channel device. The speed of a CPL circuit is strongly dependent on the “high” voltage that is applied to the gate of the n-channel device to turn it on. The higher the voltage applied at the gate, the harder the n-channel device is turned on and the lower the channel resistance. Reduced channel resistance translates into reduced RC delay. Moreover, a higher voltage applied at the gate translates into a higher output voltage produced at the output end of the circuit. The higher output voltage beneficially improves the ability of the inverter to generate a logical “0” because the Vgs of the inverter's n-channel device is larger. In summary, a higher “1” voltage results in a faster CPL circuit and, conversely, a lower “1” voltage implies a slower circuit. Unfortunately, CPL circuits are typically affected by a number of factors that can decrease the “1” voltage including coupling noise, delta-I noise, and DC voltage drop. Moreover, in silicon on insulator (SOI) devices, the voltage drop access the transistor tends to vary. This phenomenon is commonly referred to as the floating body effect or history effect and it can have a negative effect on the switching times of SOI devices. For these reasons, it is hard to model and predict the circuit speed. Scaling means applying successive generations of lower supply voltage process technology to the same circuit design. Unfortunately, scaling also means lower supply voltages, which reduce the speed of CPL circuits thereby making them less scalable.
Therefore it is highly desirable to implement a CLA in which the circuitry used to generate carry bits minimizes propagation delay without substantially increasing the cost or complexity of the circuit. It would be further desirable if the implemented circuit addressed the problems associated with conventional CPL circuitry, especially when implemented in an SOI technology.